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| Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 DESCRIPTION PT6314 is a VFD Controller/Driver IC utilizing CMOS technology providing 80 segment outputs and 24 grid outputs. It supports dot matrix displays of up to 16 columns x 2 lines, 20 columns x 2 lines or 24 columns x 2 lines. PT6314 also features a character generator ROM which stores 240 x 5 x 8 dos characters. Pin assignments and application circuits are optimized for easy PCB layout and cost saving advantages. FEATURES * * * * * * * * CMOS technology Provides up to 80 x 8 display RAM Capable of driving segment for cursor displays (48 units) Built-in oscillation circuit Parallel data input/output (switchable 4 or 8 bits) or serial data input/output Alphanumeric and symbolic display via the built-in ROM (5 x 8 dots): 240 characters Eight user-defined 5 x 8 dot character CGRAM Display contents capability: - 16 columns x 2(1) rows + 32(16) cursors - 20 columns x 2(1) rows + 40(20) cursors - 24 columns x 2(1) rows + 48(24) cursors * Custom ROM available (please contact PTC) APPLICATIONS * Electronic equipment with VFD display * Microprocessor peripherals PT6314 V1.3 -1- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 BLOCK DIAGRAM OSC1 OSC2 CLK VDD1 VDD2 VSS1 VSS2 SDO SLK /CLR LATCH TESTOUT TEST IFSEL /CS RS/STB R/W(/WR) E(/RD)/SCK SI/SO DB0 DB1 DB2 DB3 DB4 DB5 DB7 /RESET MPU DS0 DS1 DLS RL1 Oscillation Circuit Address Counter 7 7 Timing Generator 7 Display Data RAM (DDRAM) 80x8 Bits 8 24 24 Bits Shift Register 24 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR8 GR9 GR10 GR11 GR12 8 Instruction Register 8 Instruction Decoder 7 I/O Buffer 8 Data Register 8 8 7 8 Cursor Blink Control Circuit Grid Signal Driver Reset Circuit Character Generator RAM (CGRAM) 8x5x8 Bits 5 Character Generator ROM (CGROM) 248x5x8 Bits 5 Parallel to Serial Data Converter 80 Bits Latch 80 Segment Signal Driver 80 80 Bits Shift Register GR22 GR23 GR24 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG79 SG80 PT6314 V1.3 -2- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 PIN CONFIGURATION NC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 NC 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD2 VSS2 VDD1 CLK OSC2 OSC1 RESET TEST DLS DS1 DS0 R/W RS/STB E/SCK S1/S0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IFSEL MPU /CS RL1 RL2 CLR LATCH SDO SLK TESTOUT VSS1 VSS2 VDD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC PT6314 NC Note: Pin No. 38 to 71, 73 to 108, 110 to 119 are used as Segment Signal Output Pins, Pin No.120 to 143 are used as Grid Signal Output Pins and are configured according to the Tables shown in the Duty Ratio Setting Section (see pages 7 to 13). PT6314 V1.3 -3- March, 2006 NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 PIN DESCRIPTION Pin Name VDD2 VSS2 VDD1 OSCO OSC2 OSC1 /RESET TEST I/O O O I I I Description Pin No. VFD Driving Power Supply Pin 1, 36 VFD Driving Power Supply Pin 2, 35 Logic Power Supply Pin 3 Oscillation Signal Output Pin 4 Oscillation Output Pin 5 Oscillation Input Pin 6 Reset Pin When this pin is set to "0", all internal registers and commands are 7 initialized. The Segment and Grid Outputs are fixed to VDD. Test Pin 0 or floating : the Normal Operation Mode 8 1:the Test Mode is active Display Line Select Pin This pin is used to select the number of display lines when the 9 Power is ON, Reset or Resetting. 0: 1 line is selected (N="0")* 1: 2 lines are selected (N="1")* Duty Select Pin These pins set the duty ratio. The duty ratio is determined by the 10, 11 number of Grid. Read/Write (Write) Signal Pin Under the M68 Parallel Data Transfer Mode (R/W), this pin functions as the Data Transfer Select Pin. 0: Write Function 1: Read Function 12 Under the i80 parallel data Transfer Mode (/WR), this pin is Write Enable Pin. It writes data at the rising edge of this signal. Under the Serial Transfer Mode, the Read or Write function is selected by instruction and this pin is connect to either "H" or "L". Register Select/Strobe Pin Under the Parallel Transfer Mode is selected, this pin acts as the Register Select Pin. 13 0:Instruction Register (IR) 1: Data register (DR) Under Serial Data Transfer Mode, this pin acts as the Strobe Input Pin. Enable (Read)/Shift Clock Under the M68 Parallel Data Transfer Mode (E), this pin functions as the Write Enable Pin. Data is written at the falling edge. Under the i80 Parallel Data Transfer Mode (/RD), this pin functions as 14 the Read Enable Pin. When this pin is set to "LOW", data is outputted to the Data Bus. Under the Serial Data Transfer Mode, this pin functions as the Shift Clock Input Pin. Data is written at the rising edge. DLS I DS1, DS0 I R/W(/WR) I RS/STB I E(/RD)/SCK I Note: *=N is the Display Line Select Flag in "Function Set" Command PT6314 V1.3 -4March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC Pin Name SI/SO I/O I/O Description PT6314 Pin No. DB0 to DB7 I/O IFSEL MCU /CS RL1,RL2 I I I I /CLR LATCH SDO SLK O TESTOUT VSS1 GR1 to GR24 SG1 to SG80 O O O O O O Serial Input/Output Pin Under the Serial Data Transfer Mode, this pin functions as an I/O Pin. 15 Under the Parallel Data Transfer Mode, this pin may be connected to either "H" or "L" Parallel Data Input/Output Pins Under the Parallel Data Transfer Mode, these pins are used as I/O 16-23 Pin. Under the 4-bit Transfer Mode, DB4 to DB7 are used. I/F Select Pin This pin is used to select the I/F mode: Serial or Parallel Transfer 24 0: Serial Data Transfer 1: Parallel Data Transfer Interface Select Pin This pin is used to select the interface mode: i80 or M68. 25 0: i80 CPU Mode 1: M68 CPU Mode Chip Select Pin 26 When this pin is set to "L" the PT6314 is active. Segment Output Select Pin 27, 28 This pins are used to set SG1 to SG80. Extension Grid Driver Clear Signal Output Pin Active: Low The Grid Data stored in extension driver latch are outputted 29 when this pin is set to "HIGH". If this pin is set to "LOW", the extension driver outputs LOW. Extension Grid Driver Latch Enable Signal Output Pin 30 Extension Grid Driver Serial Data Output Pin 31 Extension Grid Driver Shift Clock Output Pin 32 Rising Edge: Active Test Pin for IC Testing only. 33 This pin should be "open". Logic Ground Pin 34 Grid Signal Output Pins 143-120 Segment Signal Output Pins see (1) Note: Refer to Duty Ratio Setting Section PT6314 V1.3 -5- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 DUTY RATIO SETTING DS0 and DS1 control the duty ratio of PT6314. Please refer to the table below. DS0 DS1 DUTY RATIO 0 0 1/16 (No. of GRID=16) 0 1 1/24 (No. of GRID=24) 1 0 1/20 (No. of GRID=20) 1 1 1/40 ( No. of GRID=40) Please take note that the external extension grid driver is needed to set up 1/40 duty mode. SEGMENT SETTING CONDITION 1: 2-LINE DISPLAY (N="1"), RL1="0" AND RL2="0" The number of Segment Pins is controlled by the RL1 and RL2. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. SG1 38 SG18 55 NC 72 SG2 39 SG19 56 SG35 73 SG3 40 SG20 57 SG36 74 SG4 41 SG21 58 SG37 75 SG5 42 SG22 59 SG38 76 SG6 43 SG23 60 SG39 77 SG7 44 SG24 61 SG40 78 SG8 45 SG25 62 SG41 79 SG9 46 SG26 63 SG42 80 SG10 47 SG27 64 SG43 81 SG11 48 SG28 65 SG44 82 SG12 49 SG29 66 SG45 83 SG13 50 SG30 67 SG46 84 SG14 51 SG31 68 SG47 85 SG15 52 SG32 69 SG48 86 SG16 53 SG33 70 SG49 87 SG17 54 SG34 71 SG50 88 SG68 106 SG77 116 GR18 126 SG69 107 SG78 117 GR17 127 SG70 108 SG79 118 GR16 128 NC 109 SG80 119 GR15 129 SG71 110 GR24 120 GR14 130 SG72 111 GR23 121 GR13 131 SG73 112 GR22 122 GR12 132 SG74 113 GR21 123 GR11 133 SG75 114 GR20 124 GR10 134 SG76 115 GR19 125 GR9 135 Pin Name SG51 SG52 SG53 SG54 SG55 SG56 SG57 SG58 SG59 SG60 SG61 SG62 SG63 SG64 SG65 SG66 SG67 GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 NC Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 136 137 138 139 140 141 142 143 144 PT6314 V1.3 -6- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC CONDITION 2: 2-LINE DISPLAY (N="1"), RL1="0", RL2="1" Pin Name SG40 SG39 SG38 SG37 SG36 SG35 SG34 SG33 SG32 SG31 SG30 SG29 SG28 SG27 SG26 SG25 SG24 SG68 SG69 SG70 NC SG71 SG72 SG73 SG74 SG75 SG76 Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 106 107 108 109 110 111 112 113 114 115 Pin Name SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 SG13 SG12 S G11 SG10 SG9 SG8 SG7 SG77 SG78 SG79 SG80 GR24 GR23 GR22 GR21 GR20 GR19 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 116 117 118 119 120 121 122 123 124 125 Pin Name NC SG6 SG5 SG4 SG3 SG2 SG1 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 GR18 GR17 GR16 GR15 GR14 GR13 GR12 GR11 GR10 GR9 Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 126 127 128 129 130 131 132 133 134 135 Pin Name SG51 SG52 SG53 SG54 SG55 SG56 SG57 SG58 SG59 SG60 SG61 SG62 SG63 SG64 SG65 SG66 SG67 GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 NC PT6314 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 136 137 138 139 140 141 142 143 144 PT6314 V1.3 -7- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC CONDITION 3: 2-LINE DISPLAY (N="1"), RL1="1", AND RL2="0" Pin Name SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 SG52 SG53 SG54 SG55 SG56 SG57 SG13 SG12 SG11 NC SG10 SG9 SG9 SG7 SG6 SG5 Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 106 107 108 109 110 111 112 113 114 115 Pin Name SG58 SG59 SG60 SG61 SG62 SG63 SG64 SG65 SG66 SG67 SG68 SG69 SG70 SG71 SG72 SG73 SG74 SG4 SG3 SG2 SG1 GR24 GR23 GR22 GR21 GR20 GR19 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 116 117 118 119 120 121 122 123 124 125 Pin Name NC SG75 SG76 SG77 SG78 SG79 SG80 SG40 SG39 SG38 SG37 SG36 SG35 SG34 SG33 SG32 SG31 GR18 GR17 GR16 GR15 GR14 GR13 GR12 GR11 GR10 GR9 Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 126 127 128 129 130 131 132 133 134 135 Pin Name SG30 SG29 SG28 SG27 SG26 SG25 SG24 SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 NC PT6314 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 136 137 138 139 140 141 142 143 144 PT6314 V1.3 -8- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC CONDITION 4: 2-LINE DISPLAY (N="1"), RL1="1" AND RL2="1" Pin Name SG80 SG79 SG78 SG77 SG76 SG75 SG74 SG73 SG72 SG71 SG70 SG69 SG68 SG67 SG66 SG65 SG64 SG13 SG12 SG11 NC SG10 SG9 SG9 SG7 SG6 SG5 Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 106 107 108 109 110 111 112 113 114 115 Pin Name SG63 SG62 SG61 SG60 SG59 SG58 SG57 SG56 SG55 SG54 SG53 SG52 SG51 SG50 SG49 SG48 SG47 SG4 SG3 SG2 SG1 GR24 GR23 GR22 GR21 GR20 GR19 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 116 117 118 119 120 121 122 123 124 125 Pin Name NC SG75 SG76 SG77 SG78 SG79 SG80 SG40 SG39 SG38 SG37 SG36 SG35 SG34 SG33 SG32 SG31 GR18 GR17 GR16 GR15 GR14 GR13 GR12 GR11 GR10 GR9 Pin No. 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 126 127 128 129 130 131 132 133 134 135 Pin Name SG30 SG29 SG28 SG27 SG26 SG25 SG24 SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 NC PT6314 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 136 137 138 139 140 141 142 143 144 PT6314 V1.3 -9- March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC CONDITION 5:1-LINE DISPLAY (N="0"), RL2="0" The RL1 setting is irrelevant. The table below shows the Segment Pin setting. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name SG1 38 SG18 55 NC 72 * SG2 39 SG19 56 SG35 73 * SG3 40 SG20 57 SG36 74 * SG4 41 SG21 58 SG37 75 * SG5 42 SG22 59 SG38 76 * SG6 43 SG23 60 SG39 77 * SG7 44 SG24 61 SG40 78 * SG8 45 SG25 62 * 79 * SG9 46 SG26 63 * 80 * SG10 47 SG27 64 * 81 * SG11 48 SG28 65 * 82 * SG12 49 SG29 66 * 83 * SG13 50 S G30 67 * 84 * SG14 51 SG31 68 * 85 * SG15 52 SG32 69 * 86 * SG16 53 SG33 70 * 87 * SG17 54 SG34 71 * 88 * * 106 * 116 GR18 126 GR8 * 107 * 117 GR17 127 GR7 * 108 * 118 GR16 128 GR6 NC 109 * 119 GR15 129 GR5 * 110 GR24 120 GR14 130 GR4 * 111 GR23 121 GR13 131 GR3 * 112 GR22 122 GR12 132 GR2 * 113 GR21 123 GR11 133 GR1 * 114 GR20 124 GR10 134 NC * 115 GR19 125 GR9 135 Note: *=Not Used PT6314 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 136 137 138 139 140 141 142 143 144 PT6314 V1.3 - 10 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC CONDITION 6: 1-LINE DISPLAY, RL2="1" The RL1 setting is irrelevant. Segment Output Pin settings are as follows: Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. SG40 38 SG23 55 NC 72 SG39 39 SG22 56 SG6 73 SG38 40 SG21 57 SG5 74 SG37 41 SG20 58 SG4 75 SG36 42 SG19 59 SG3 76 SG35 43 SG18 60 SG2 77 SG34 44 SG17 61 SG1 78 SG33 45 SG16 62 * 79 SG32 46 SG15 63 * 80 SG31 47 SG14 64 * 81 SG30 48 SG13 65 * 82 SG29 49 SG12 66 * 83 SG28 50 S G11 67 * 84 SG27 51 SG10 68 * 85 SG26 52 SG9 69 * 86 SG25 53 SG8 70 * 87 SG24 54 SG7 71 * 88 * 106 * 116 GR18 126 * 107 * 117 GR17 127 * 108 * 118 GR16 128 NC 109 * 119 GR15 129 * 110 GR24 120 GR14 130 * 111 GR23 121 GR13 131 * 112 GR22 122 GR12 132 * 113 GR21 123 GR11 133 * 114 GR20 124 GR10 134 * 115 GR19 125 GR9 135 Note: *=Not Used Pin Name * * * * * * * * * * * * * * * * * GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 NC PT6314 Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 136 137 138 139 140 141 142 143 144 PT6314 V1.3 - 11 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 VFD DISPLAY PT6314 supports 24 character x 2 display lines. Please refer to the diagram below for VFD Display construction. SG1 SG40 SG41 SG80 GR1 GR2 GR24 SG1 SG5 SG6 SG10 SG71 SG75 SG76 SG80 PT6314 V1.3 - 12 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 FUNCTION DESCRIPTION BLOCK FUNCTIONS CPU INTERFACE PT6314 provides either 4 or 8 bits parallel or serial interface. These interface modes may be selected using the IFSEL Pin (Pin No.24) as follows: IFSEL Setting "0" "1" Data Transfer Mode Serial Data Transfer Parallel Data Transfer REGISTERS (INSTRUCTION REGISTER & DATA REGISTER) PT6314 supports two 8-bit registers, namely: an Instruction Register (IR) and a Data Register (DR) which may be selected using the Register Selector (RS) Signal. Please refer to Table below. IFSEL 0 1 /CS /CS /CS RS STB RS E/SCK SCK E/(/RD) R/W * R/D(/WR) MCU * MCU SI/SO SI/SO * DBn * DBn Note: *=This pin must be kept in either "HIGH" or "LOW" State. The Instruction Register (IR) stores (1) instruction codes (i.e. display clear and cursor shift), (2) Display Data RAM (DDRAM) Address Information and (3) Character Generator RAM (CGRAM). It can only be written from the MCU. The Data Register (DR) acts as a temporary storage for (1) data to be written into the DDRAM or CGRAM and (2) data to be read from the DDRAM or CGRAM. Data written into the DR from the MCU is automatically written into the DDRAM or CGRAM by internal operation. When the data stored in DR is read by the MCU, data transfer is completed. After the completion of the data transfer (that is, after the MCU has finished reading the first set of data), the DDRAM or CGRAM data in the next address is sent to the DR. The MCU then again performs its Read operation for the next set of data. PT6314 V1.3 - 13 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC BUSY FLAG (READ BF FLAG) The Busy Flag Data (DB7) always outputs "0". PT6314 ADDRESS COUNTER (AC) The Address Counter (AC) designates the addresses of the DDRAM and CGRAM. When an address of instruction is written into the Instruction Register, the address information is sent from the Instruction Register (IR) to the Address Counter. The selection of either the DRAM or CGRAM is also determined concurrently by the instruction. After writing into the DDRAM or CGRAM, the Address Counter is increased by 1. (The Address Counter is decreased by 1 after data is read from the DDRAM or CGRAM.) The contents of the Address Counter are then outputted to the DB0~DB6 when RS="0" and R/W="1". Please refer to the table below. Common RS 0 0 1 1 M68 R/W 0 1 0 1 I80 /RD 1 0 1 0 /WR 0 1 0 1 Register Selection Write IR Data as internal operation (i.e. display clear) Read data to busy flag (DB7) and Address Counter (DB6 to DB0) Write DR Data (DRDDRAM/CGRAM) Read DR Data (DDRAM/CGRAMDR) PT6314 V1.3 - 14 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 DISPLAY DATA RAM (DDRAM) The Display Data RAM (DDRAM) stores the display data shown in the 8-bit character codes. When expanded the Display Data RAM supports a capacity of 80 x 8 bits or 80 characters. The area in the DDRAM that is not in used for display may be used as general data RAM. AC High Order Bits AC6 AC5 hexadecimal AC4 Low Order Bits AC3 AC2 hexadecimal AC1 AC0 Please note that the DDRAM Address (ADD) is set in the Address Counter(AC) as hexadecimal. Example: DDRAM Address "26": 0 2 1 0 0 6 1 1 0 N="0" 1-LINE DISPLAY, 80 CHARACTERS Display Position Digit 1 DDRAM Address(hexadecimal) 00 2 01 3 02 4 03 5 04 6 05 ...... ...... 79 4E 80 4F N="0" 1-LINE DISPLAY, LESS THAN 80 CHARACTERS In cases when there are less than 80 display characters, the display begins at the head position. For example, if only one piece of PT6314 is being used, 24 characters are displayed. When the display shift operation is performed, the DDRAM address shifts, please refer to the figure below. Display Position Digit 1 DDRAM Address(hexadecimal) 00 For Shift-Left For Shift-Right 01 4F 2 01 02 00 3 02 03 01 4 03 04 02 5 04 05 03 6 05 06 04 ...... ...... ...... ...... 23 16 17 15 24 17 18 16 N="1" 2-LINE DISPLAY, 40 CHARACTERS Display Position Digit DDRAM Address (hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 ...... ...... ...... 39 26 66 40 27 67 PT6314 V1.3 - 15 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC N="1" 2-LINE DISPLAY, LESS THAN 40 CHARACTERS PT6314 In cases when the number of display characters is less than 40 x 2 lines, the two lines are displayed from the head. The line end address and the second line start address are not consecutive. For example, if only one PT6314 is being used, 24 characters x 2 lines are displayed. When the display shift operation is performed, the DDRAM address shifts. Display Position Digit DDRAM Address (hexadecimal) For Shift-Left For Shift-Right 1 00 40 01 41 27 67 2 01 41 02 42 00 40 3 02 42 03 43 01 41 4 03 43 04 44 02 42 5 04 44 05 45 03 43 6 05 45 06 46 04 44 ...... ...... ...... ...... ...... ...... ...... 23 16 56 17 57 15 55 24 17 57 18 58 16 56 N="1":2-LINE DISPLAY, 40 CHARACTERS PT6314 can be extended using one of the 16 output extension drivers as GRID. Under this condition, a 40-character x 2 lines display may be constructed. Display Position Digit DDRAM Address (hexadecimal) Digit For Shift-Left Digit For Shift-Right 1 00 40 1 01 41 1 27 67 2 01 41 2 02 42 2 00 40 3 02 42 3 03 43 3 01 41 4 03 43 4 04 44 4 02 42 ...... ...... ...... ...... ...... ...... ...... ...... ...... 23 16 56 23 17 57 23 15 55 24 17 57 24 18 58 24 16 56 25 18 58 25 19 59 ...... ...... ...... ...... ...... ...... 39 26 66 39 27 67 40 27 67 40 00 40 PT6314 Display 25 ...... 39 40 17 ...... 25 26 57 ...... 65 66 Extension Driver Display PT6314 V1.3 - 16 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 CHARACTER GENERATOR ROM (CGROM) The CGROM is the Read Only Memory (ROM) responsible for the generation of 5 x 8 dots character patterns from 8-bit character codes. A total of up to 240 character patterns can be generated. Please note that Character Codes -- 00H to 0FH are allocated to the CGRAM. CHARACTER GENERATOR RAM (CGRAM) The Character Generator RAM (CGRAM) allows the user to reconstruct the character patterns from 8-bit by software programming. Eight character patterns can be written and constructed using 5 x 8 dots. Areas that are not used for display purposes may be used as general data RAM. The table below shows the relationship between the CGRAM Address, Character Code (DDRAM) and the 5x7 (cursor included) dot character patterns (CGRAM). Character Code (DDRAM Data) D7 D6 D5 D4 D3 D2 D1 D0 High Order Bit Low Order Bit 0 0 0 0 X 0 0 0 CGRAM Address A5 A4 A3 A2 A1 A0 High Order Bit Low Order Bit 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D7 D6 D5 High Order Bit X X X CGRAM Data D4 D3 D2 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 D1 D0 Low Order Bit 1 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 Character Pattern No. 1 Cursor Position 0 0 0 0 X 0 0 1 X X X Character Pattern No. 2 Cursor Position 0 0 0 0 X 1 1 1 X X X Character Pattern No. 8 Cursor Position Notes: 1. X= Irrelevant 2. Character Code Bits 0 to 2 correspond to the CGRAM Address Bits 3 to 5 (3 bits: 8 type). 3. CGRAM Address Bits 0 to 2 determine the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position at 0 as the cursor display. If the 8th line data is "1" all the 1 bits will light up the 8th line regardless of the cursor presence. 4. Character pattern row position corresponds to the CGRAM data bits 0 to 4. (bit 4 is positioned at the left) 5. The CGRAM character patterns are selected when the character code bits 4 to 7 are all set to "0". The Character Code Bit 3 is irrelevant, the "P" Display shown above (Character Pattern No. 1) can be selected by either character Code 00H or 07H. 6. When CGRAM Data="1" the Display is turned ON. When CGRAM data="0" display is turned OFF. PT6314 V1.3 - 17 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 TIMING GENERATION CIRCUIT Timing signals for internal circuit operations(i.e. DDRAM, CGRAM) are generated by the Timing Generation Circuit. The Display RAM Read timing and the MCU access internal operation timing are generated separately in order to avoid interferences. Thus, for example, when data is being written to the DDRAM, no undesirable interference occur (i.e. flickering in areas other than the display location) VFD DRIVER CIRCUIT The VFD Driver Circuit is composed of 24 grid and 80 segment signal drivers. During power On, the character font and number of digits are selected by the hardware (DS0 and DS1), the required grid signal drivers automatically output drive waveforms while the other grid signal drivers continue to output non-selected waveforms. The serial data sent is latched when the display data character pattern corresponding to the last address of the display data RAM (DDRAM). Since the serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, PT6314 drives from the head display. CURSOR/BLINK CONTROL CIRCUIT Cursor and Character blinking are generated by the Cursor / Blink Control Circuit. The cursor or the blinking will appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC). For example, when the address counter is 08H, the cursor position is displayed at DDRAM Address 08H. AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC 0 0 0 1 0 0 0 FOR 1-LINE DISPLAY: Display position Digit DDRAM Address(hexadecimal) 1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B Cursor Position FOR 2-LINE DISPLAY: Display position Digit DDRAM Address(hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0A 4A 12 0B 4B Cursor Position Note: The cursor or blinking appears when the address counter (AC) selects the Character Generator RAM (CGRAM). The cursor and blinking become meaningless. When the Address Counter is a CGRAM Address, the cursor or the blinking is displayed in a meaningless position. PT6314 V1.3 - 18 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 CPU INTERFACE (DATA TRANSFER) M68 PARALLEL DATA TRANSFER The M68 type of parallel data transfer is selected when IFSEL is set to "1" and MCU is set to "0" Under this mode, the PT6314 can interface with the CPU in 4 or 8 bits . Please take note that the internal registers are composed of 8 bits. During data transfer in 4 bits, DB4 to DB7 performs the data transfer operation two times, the DB0 to DB3 must be set to either "H" or "L". The higher order 4 bits (D4 to D7) are initially transferred followed by the lower order 4 bits (D0 toD3). please refer to the diagrams below. 4-Bit M68 TYPE PARALLEL Data Transfer RS R/W E DB7 DB6 DB5 DB4 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 BF=0 IR6 IR5 IR4 IR3 IR2 IR1 IR0 D7 D6 D5 D4 D3 D2 D1 D0 Write Instruction Write Instruction Read Instruction Write Data PT6314 V1.3 - 19 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC 8-BIT M68 TYPE PARALLEL DATA TRANSFER RS PT6314 R/W E DB7 DB6 IR7 IR6 IR7 IR6 BF="0" IR6 D7 D6 DB0 IR0 Write Instruction IR0 Write Instruction IR0 Read Instruction D0 Write Data I80 TYPE PARALLEL DATA TRANSFER The i80 type of parallel data transfer mode is selected when IFSEL is set to "1"and MCU is set to "0". A type of pipeline process is performed between LSIs via the bus holder attached to the internal data bus whenever data is sent from the MCU. It is important to take note that certain restrictions exists in the read sequence of this display data RAM. The data of the specified address is not generated by the read instructions issued immediately after the address setup. This data is generated in the when the data is read the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is selected. Please refer to the diagrams below. PT6314 V1.3 - 20 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC Writing MPU /WR PT6314 DATA Internal Timing Bus Holder N LATCH N+1 N+2 N+3 N Write Signal N+1 N+2 N+3 Reading MPU /WR /RD DATA Internal Timing Address Preset Read Signal N N n n+1 Column Address Bus Holder PRESET N N Address Set #n Dummy Read INCRE MENT N+1 N+2 n+1 n+2 Data Read #n+1 n Data Read #n PT6314 V1.3 - 21 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC SERIAL DATA TRANSFER PT6314 PT6314 supports serial data transfer mode. When data is written, it can be inputted when the Strobe goes to "0". The first byte -- Start Byte consists of a total of 8 bits : the Synchronous bits (bit 1 - bit 5), R/W (bit 6), RS (bit 7) and bit 8. The register will be selected (IR or DR) by the RS (bit 7) and the data write or read is selected by R/W (bit 6 = "0") in this byte. The Start Byte is followed by the 8-bit Instruction Byte. The Start Byte selects which is process is to be inputted first: read the Busy Flag + Address Counter (AC6 to AC0) or read the data which was written in the DDRAM or CGRAM. Data is outputted at the falling edge of the shift clock. Data Write STB 1 SCK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SI "1" "1" "1" "1" "1" R/W RS "0" D7 D6 D5 D4 D3 D2 D1 D0 Synchronous Bits Start Byte Instruction/Data Data Read STB Wait Time: tWAIT 1s 1 SCK BF "0" 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 SI/SO "1" "1" "1" "1" "1" R/W RS "0" IR6 IR5 IR4 IR3 IR2 IR1 IR0 Synchronous Bits Start Byte Read Data PT6314 V1.3 - 22 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 INSTRUCTIONS Instruction Clear Display Cursor Home Entry Mode Set Display ON/Off Cursor or Display Shift Function Set CGRAM Address Set DDRAM Address Set Read Busy Flag & Address Write Data to CGRAM or DDRAM Read Data to CGRAM or DDRAM RS 0 0 R/ W 0 0 DB 7 0 0 DB6 0 0 DB5 0 0 DB 4 0 0 DB 3 0 0 DB2 0 0 DB1 0 1 DB0 1 X Description Clear all display, and sets DDRAM address at 00H Set DDRAM address at 00H. Also returns the display being shifted to the original position. DDRAM contents remain unchanged. Sets the cursor direction and specifies display shift. These operations are performed during the writing/reading of data. Sets all display on/off (D) Cursor on/off (C). Cursor blinks on character position (B) Shifts display or cursor, also keeps DDRAM contents. Sets data length (in parallel data transfer) and number of line. Sets address of CGRAM. After which CGRAM data is transferred. Sets DDRAM address, after which DDRAM data is transferred. Reads busy flag (BF) and address counter. BF="0" Writes data into the CGRAM or DDRAM. Reads data from CGRAM or DDRAM 0 0 0 0 0 0 0 1 1/D S 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 BF="0" 0 0 0 1 0 0 1 0 1 DL 1 SC N D R/L X ACG C X BR1 B X BR0 ADD ACC Write Data Read DR Data Notes: 1. I/D="1": Increment I/D="0": Decrement 2. S="1": Display Shift Enabled S="0": Cursor Shift Enabled 3. D, C, B="1": Turn On D, C, B="0": Turn OFF 4. S/C="1": Display Shift S/C="0": Cursor Shift 5. R/L="1": Shift to the Right R/L="0": Shift to the Left 6. DL="1": 8 Bits DL="0": 4 Bits 7. N="0": 1-Line Display N="1": 2-Line Display 8. BR1, BR0="00": 100% BR1, BR0="10": 50% BR1, BR0="01": 75% BR1, BR0="11": 25% 9. X=Irrelevant 10. DDRAM: Display Data RAM 11. CGRAM: Character Generator RAM 12. ACG: CGRAM Address 13. ADD: DDRAM Address 14. ACC: Address Counter PT6314 V1.3 - 23 March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 "CLEAR DISPLAY" INSTRUCTION CODE During Reset, RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 The CLEAR DISPLAY Instruction performs the following operations: 1. Fills all Display Data RAM (DDRAM) location with 20H (Blank Character). 2. Clears the contents of the Address Counter (ACC) to 00H. 3. Sets the display for Zero Character Shift (Returns to original position.) 4. Sets the Address Counter to point to the Display Data RAM (DDRAM). 5. If the cursor is displayed, this instruction will move the cursor to the left most character in the upper display line. 6. Sets the Address Counter (ACC) to increment on each access of the DDRAM or CGRAM. "CURSOR HOME" INSTRUCTION RS CODE 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 X The CURSOR HOME Instruction performs the following operations: 1. Clears the contents of the Address Counter (ACC) to 00H. 2. Sets the Address Counter to point to the Display Data RAM (DDRAM). 3. Sets the Display for Zero Character Shift (Returns to the original position). 4. If the cursor is displayed, this instruction moves the cursor to the left most character in the upper line display. PT6314 V1.3 - 24 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 "ENTRY MODE" INSTRUCTION CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 I/D S The "I/D" Bit provides a way to modify the contents of the address counter after every access to the DDRAM or CGRAM. When I/D is set to "1" the Address Counter is incremented after the DDRAM or CGRAM has been accessed. When the I/D is set to "0" the Address Counter is decremented after the DDRAM or CGRAM has been accessed. The "S" Bit controls the display or cursor shift after each read or write operation to the DDRAM. If S is set to "1" the "Display Shift" Instruction is enabled. If the S is set to "0" the "Cursor Shift" Instruction is enabled. The direction in which the display is shifted is opposite to that of the cursor. For example, if S="0" and I/D="1" the cursor will shift one character to the right after the MCU writes to the DDRAM. But, if the S="1" and I/D="1" the display will shift one character to the left and the cursor will remain in the same position in the panel display. The cursor has already been shifted in the direction selected by the I/D during the reading of the DDRAM irrespective of the value of "S". Reading and writing the CGRAM always shifts the cursor. Both lines are shifted at the same time. The table below shows the various cursor and display shift movements by the "Entry Mode Set". I/D 0 1 0 1 S 0 0 1 1 After Writing DDRAM Data Cursor moves one character to the left. Cursor moves one character to the right. Display shifts one character to the right without any cursor movement. Display shifts one character to the left without any cursor movement. After Reading DDRAM Data Cursor moves one character to the left. Cursor moves one character to the right. Cursor moves one character to the left. Cursor moves one character to the right. During Reset, DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 1 DB0 0 PT6314 V1.3 - 25 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 "DISPLAY ON/OFF" INSTRUCTION CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 D C B The above instruction controls the various display features: D="1": Display ON D="0": Display OFF C="1": Cursor ON C="0": Cursor OFF B="1": Blinking ON B="0": Blinking OFF Blinking is achieved by alternating a normal and an all "ON" display of a character. The cursor blinks with a frequency of approximately 1 Hz and 50% duty. BLINK (1Hz) Cursor Line During Reset, DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 0 "Cursor or Display Shift" Instruction CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 S/C R/L X X The instruction above will shift the display and/or move the cursor one character to the left or right, without DDRAM reading or writing. "S/C" Bit selects between the movement of both cursor and display or the movement of the cursor alone. When "S/C"="1" the cursor and the display are both shifted. When "S/C"="0" only the cursor is shifted. The "R/L" Bit selects the left or right movement direction of the cursor and/or display. When "R/L"="1" the cursor and/or display is shifted one character to the right. When "R/L" is "0" the cursor and/or character is shifted to the left. PT6314 V1.3 - 26 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC The table below summarizes display and cursor shift and movement. PT6314 S/C 0 0 1 1 R/L 0 1 0 1 Cursor Move one character to the left. Move one character to the right. Move one character to the left with display Move one character to the right with display Display No shift No shift Shift one character to the left. Shift one character to the right. PT6314 V1.3 - 27 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 "FUNCTION SET" INSTRUCTION CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 DL N X BR1 BR0 The instruction above sets the data length of the data bus lines. This instruction initializes the system, and must be the first instructed executed after power is turned ON. The "DL" and "N" settings are described below: "DL"="1": 8-bit MCU Interface using DB7 to DB0 "DL"="0": 4-bit MCU Interface using DB7 to DB4 "N"="0": 1-Line Display using SG1 to SG40. (SG41 to SG80 are fixed at "Low Level") "N"="1":2-Line Display using SG1 to SG80 x = Not Relevant BR1 and BR0 flags are used to modulate the pulse width of the Segment Output thereby controlling the VFD brightness. BR1 BR0 Brightness tp 0 0 100% tDSP x 1.00 0 1 75% tDSP x 0.75 1 0 50% tDSP x 0.5 1 1 25% tDSP x 0.25 tDSP200s, tBLK10s tDSP tp T SGn tBLK tBLK G1 Gn where n = number of Grid, T =n x (tDSP + tBLK) During Reset, DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 PT6314 V1.3 - 28 March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 "CGRAM ADDRESS SET" INSTRUCTION CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 A A A A A A The above instruction is used to (1) load new 6-bit address into the address counter, and (2) set the address counter to point to the CGRAM. Once the "CGRAM Address Set" instructions has been executed, the contents of the address counter (ACC) is automatically modified after every access of the CGRAM, as determined by the "Entry Mode Set" instruction. The active width of the address counter, when it is addressing the CGRAM is 6 bits. The counter will wrap around from 00H to 3FH if more than 64 bytes of data is written to the CGRAM. During Reset, this instruction is irrelevant. "DDRAM ADDRESS SET" INSTRUCTION CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 A A A A A A A The above instruction is used to (1) load new 7 bits address into the address counter, and (2) set the address counter to point to the CGRAM. Once the "DDRAM Address Set" instruction has been executed, the contents of the address counter (ACC) is automatically modified after every access of the DDRAM, as determined by the "Entry Mode Set" instruction. The valid DDRAM address range is given below. Line Display 1st Line 2nd Line During Reset, this instruction is irrelevant. Number of Characters 40 40 Address Range 00H to 27H 40H to 67H "READ BUSY FLAG AND ADDRESS" INSTRUCTION CODE RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 BF A A A A A A A The above instruction reads the Busy Flag (BF) * and the value of the address counter in binary "AAAAAAA". This address counter is used by the CGRAM and DDRAM addresses and its values are determined by the previous instruction. Address counter contents are the same as that of "CGRAM Address Set" and "DDRAM Address Set" Instructions. Note: * The Busy Flag (BF) = "0" PT6314 V1.3 - 29 March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 "WRITE DATA TO CGRAM OR DDRAM" INSTRUCTION CODE RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 D D D D D D D D High Order Bit Low Order Bit The above instruction write 8 bits binary data "DDDDDDDD" to the CGRAM or DDRAM. Writing into the CGRAM or DDRAM is determined by the previous instruction of the "CGRAM or DDRAM Address Set". After a data is written, the value of the address is automatically increased or decreased by one in accordance to the selection made by the "Entry Mode Set". The "Entry Mode Set" also determines the display shift. "READ DATA FROM CGRAM OR DDRAM" INSTRUCTION CODE RS 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 D D D D D D D D High Order Bit Low Order Bit The above instruction reads the 8 bits binary data "DDDDDDDD" from the CGRAM or DDRAM. The "CGRAM or DDRAM Address Set" instruction must be executed first before this instruction can be entered. If the "CGRAM or DDRAM Address Set" is not executed prior to the "READ Data from CGRAM or DDRAM" then the first READ data becomes invalid. When "Read" Instructions are serially executed, the next address data is normally read from the second "Read". Before the cursor shifts by the "Cursor or Display Shift" Instruction, the address set instruction do not need to be executed before the read instruction (only applies to DDRAM). The operation of the cursor shift instruction is the same as the "DDRAM Address Set" Instruction. After reading one data, the value of the address is automatically increased or decreased by 1 in accordance to the selection made in the "Entry Mode". Please note that the address counter is automatically increased or decreased by 1 after "Write Data to CGRAM or DDRAM" Instruction is executed. At this moment, the address counter's target data cannot be read if the "Read Data from CGRAM or DDRAM" Instruction is executed. Thus, to read data correctly, the "Address Set" or "Cursor Shift" (if Read Data from DDRAM only) Instruction must be executed before reading. PT6314 V1.3 - 30 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 POWER ON RESET When PT6314 is initialized, the internal status after power supply has been reset is as follows: 1. Display Clear: 20H (space code) fills the DDRAM 2. Address Counter is set to 00H 3. Address Counter is pointed to the DDRAM 4. Display ON/OFF: D=0, C=0, B=0 (Display OFF) 5. Entry Mode Set: I/D=1, S=0 (Increment, Cursor Shifts are enabled) 6. Function Set: DL=1, N=1 (8-Bit MCU Interface, 2-Line Display are enabled.) 7. Brightness Control: BR0=BR1=0 (Brightness = 100%) For the MCU Interface and Duty Ratio Selection, please refer to the table below. Pin Name TEST IFSEL DS1 0 X X 1 0 X 1 1 X 1 1 1 1 X X X X 0 0 1 1 DS0 X X X 0 1 0 1 Function Self Test Mode Serial Interface Parallel Interface Duty=1/16 (16Cx1 or 2L Display) Duty=1/20 (20Cx1 or 2L Display) Duty=1/24 (24Cx1 or 2L Display) Duty=1/40 (40Cx1 or 2L Display) Remarks This is effective specially after long usage. SI/SO, SCK, STB RS, E, R/W, DB7 to DB4 or DB7 to DB0 It does not need to use the extension driver. The number of display lines is selected by instruction. Extension driver must be used. The number of display lines is selected by instruction. The above table shows the relationship between the status of PT6314 and the pin states during RESET. PT6314 V1.3 - 31 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 CGRAM STROKE FLOWCHART Set CGRAM Address Increment or Decrement Set CGRAM Address Read Read Data From CGRAM Write Write Data To CGRAM DDRAM STROKE FLOWCHART Set DDRAM Address Increment or Decrement Set DDRAM Address Read Read Data From DDRAM Write Write Data To DDRAM PT6314 V1.3 - 32 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta=+25, Vss1=Vss2=0V) Parameter Symbol Logic power supply voltage VDD1 Logic input voltage Vi Logic output voltage Vo Driver power supply voltage VDD2 Driver output voltage VO2 IOL2S Segment IOH2S Driver output current IOL2G Grid IOH2G Power dissipation PD Operating temperature Topr Storage temperature Tstg Rating -0.5 to +6.0 -0.5 to VDD1 + 0.5 -0.5 to VDD1 +0.5 -0.5 to +60 -0.5 to VDD2 + 0.5 +10 -4 +10 -20 1.2 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA W RECOMMENDED OPERATING RANGE (Unless otherwise specified, Ta=+25, Vss1=Vss2=0V) Parameter Symbol Min. Logic power supply voltage VDD1 4.5 Logic system input voltage VIN 0 Driver power supply voltage VDD2 20 IOL2S Segment IOH2S Drive output current IOL2G Grid IOH2G - Typ. 5.0 - Max. 5.5 VDD1 50 +5 -2 +5 -15 Unit V V V mA mA mA mA Note: It is recommended that the order in which power is to be applied to the chipset is as follows: VDD1 Input VDD2 PT6314 V1.3 - 33 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta=-40 to +85, VDD1=5.0V, VDD2=50V, VSS1=VSS2=0V) Parameter High level input voltage 1 Low level input voltage 1 High level input voltage 2 Low level input voltage 2 High level output voltage (LOGIC) Low level output voltage (LOGIC) High level input current High level leakage current Low level leakage current High level output voltage (DRIVER) Low level output voltage (DRIVER) Current consumption Condition Min. Typ. Max. Logic, Expect E/SCK,RESET 0.7VDD1 Logic, Expect E/SCK,RESET, 0.3 VDD1 VIL1 DLS VIH2 E/SCK, RESET 0.8VDD1 VIL2 E/SCK, RESET,DLS 0.2 VDD1 DBn, SI/SO, SDO, SLK, VDD1-0.5 VOH1 LATCH,/CLR, IOH1=-0.1mA DBn, SI/SO, SDO, SLK, VSS1+0.5 VOL1 LATCH,/CLR, IOL1=+0.1mA IIH TEST, VIN=VDD1 20 500 ILOH Logic, VINOUT=VDD1 1.0 ILOL Logic, VINOUT=VSS1 -1.0 VOH2S1 SG1to SG80, IOH2=-1mA 46 VOH2S2 SG1 to SG80, IOH2=-2mA 45 VOH2G GR1 to GR24, IOL2=-15mA 45 SG1 to SG80, GR1 to GR24 5 VOL2 IOL2=1mA IDD1 Logic 100 IDD2 Driver 100 Symbol VIH1 Unit V V V V V V A A A V V V V A A Note: The Typical (Typ.) Value is a reference value when Ta=25. SWITCHING CHARACTERISTICS (Unless otherwise specified, Ta=-40 to +85, VDD1=5.0 10%) Parameter Symbol Condition Oscillation frequency Fosc R=56K Operation frequency fc OSC1 External Clock Rise time TTLH1 SG1 to SG80, CL=50pF Rise time (see Note 2) TTLH2 GR1 to GR24, CL=50pF SG1 to SG80, GR1 to GR24 Fall time TTHL CL=50pF Min. Typ. Max. Unit 392 560 728 KHz 450 560 900 KHz 1.0 s 1.0 s 1.0 s PT6314 V1.3 - 34 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 SWITCHING TIMING TT HL 90% SGn, GRn 10% TT LH1, 2 90% 10% TIMING 1 REQUIREMENTS (Unless otherwise specified, Ta=-40 to +85) M68 Interface Parallel Data Transfer: Write (VDD1=5.0V 10%) Parameter Symbol Condition E E Enable cycle time tCYCE Enable "H" pulse width PWEH E Enable "L" pulse width PWEL E RS,R/W E RS, R/W - E setup time tAS E RS,R/W RS, R/W - E hold time tAH Data E Data setup time tDS E Data Data hold time tDH Reset pulse width tWRE M68 Interface Parallel Data Transfer: Read (VDD1=5.010%) Parameter Symbol Condition E E Enable cycle time tCYCE Enable "H" pulse width PWEH E Enable "L" pulse width PWEL E RS,R/W E RS, R/W - E setup time tAS E RS,R/W RS, R/W - E hold time tAH E Data Data delay time tDD E Data Data hold time tDHR Min. Typ. Max. Unit 500 ns 230 ns 230 ns 20 ns 10 ns 80 ns 10 ns 500 ns Min. Typ. Max. Unit 500 ns 230 ns 230 ns 20 ns 10 ns 160 ns 5 ns PT6314 V1.3 - 35 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PARALLEL I/F (M68 INPUT) RS PT6314 R/W tAS PWEH E tDS DB0 to DB7 tDH tAH PWEL /CS VALID DATA tCYCE PARALLEL I/F (M68 OUTPUT) RS R/W tAS PWE E tDD DB0 to DB7 tDHR tAH PWE /CS VALID DATA tCYCE Notes: 1. Input Signal Rise Time and Fall Time (tF, tR) < 15ns. 2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference. 3. PWEH is the overlap between /CS="L" and E. PT6314 V1.3 - 36 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 TIMING 2 REQUIREMENTS (Unless otherwise specified, Ta=-40 To +85) I80 Interface Parallel Data Transfer: Write (VDD1=5.0 10%) Parameter Symbol Condition RS hold time tRH8 RS setup time tRS8 System cycle time tCYC8 Control "L" pulse width (WR) tCCLW /WR Control "L" pulse width (RD) tCCLR /RD Control "H" pulse width (RD) tCCHW /WR Control "H" pulse width (RD) tCCHR /RD Data setup time tDS8 D0 to D7 Data hold time tDH8 Do to D7 RD access time tACC8 Do to D7, CL=100pF Output disable time tOH8 Do to D7, CL=100pF Reset pulse width tWRE Parallel I/F (I80) RS tRHS tr /CS tRS8 /W R, /RD tr D0 to D7 (WRITE) tO HS D0 to D7 (READ) tACCS tO SS tO HS tCCLR, tCCLW tCYCS tCCHR, tCCHW tr Min. Typ. Max. Unit 10 ns 10 ns 168 ns 30 ns 70 ns 100 ns 70 ns 55 ns 55 ns 70 ns 5 ns 500 ns Notes: 1. Input signal rise time and fall time (tF, tR) < 15ns 2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference. 3. tCCLW and tCCLR are specified as the overlap between /CS="L" /WR and /RD="L" PT6314 V1.3 - 37 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 TIMING 3 REQUIREMENTS (Unless otherwise specified, Ta=-40 to +85) Serial Data Transfer: (VDD1=5V10%) Parameter Symbol Shift clock cycle tCYK High level shift clock pulse width tWHK Low level shift clock pulse width tWLK Shift clock hold time tHSTBK Data setup time tDS Data hold time tDH STB hold time tDKSTB STB pulse width tWSTB Wait time tWAIT Output data delay time tODD Output data hold time tODH Reset pulse width tWRE Condition SCK SCK SCK STB SCK Data SCK SCK Data SCK STB 8th CLK 1st CLK SCK Data SCK Data Min. Typ. Max. Unit 500 ns 200 ns 200 ns 100 ns 100 ns 100 ns 500 ns 500 ns 1 ns 150 ns 5 ns 500 ns SERIAL I/F (INPUT) tWSTB STB tCYK tHSTBK SCK tDS SI tDH tWHK tWLK tCKSTB PT6314 V1.3 - 38 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC SERIAL I/F (OUTPUT) tWSTB PT6314 STB tCYK tHSTBK SCK tODD SO Notes: 1. Input Signal Rise Time and Fall Time (tF, tR) < 15 ns. 2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference. tWHK tWLK tDKSTB tODH AC MEASUREMENT POINT VIH INPUT VOH OUTPUT RESET /RESET tW RE VOL VIL PT6314 V1.3 - 39 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 TIMING 4 REQUIREMENTS (Unless otherwise specified, Ta=-40 to +85) M68 & I80 Serial Interface Common Timing: Power ON RESET (VDD1=5.010%) Parameter Symbol Condition Min. Typ. Max. Unit Reset time tRES VDD 100 s VDD rising time trDD VDD 1 s VDD off width tOFF VDD 1 ms trDD VDD tRES 4.5V 0.2V tOFF Internal Reset Time PT6314 V1.3 - 40 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 ENGLISH/JAPANESE CHARACTER FONT TABLE (PT6314-001) PT6314 V1.3 - 41 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 ENGLISH/EUROPEAN CHARACTER FONT TABLE (PT6314-002) PT6314 V1.3 - 42 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 SPECIAL CHARACTER FONT TABLE (PT6314-16) PT6314 V1.3 - 43 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 APPLICATION CIRCUIT 1: SERIAL INTERFACE 143 GR1 142 GR2 141 GR3 120 GR24 5 x 8 dot x 24Grid x 2 Line VFD SG2 SG3 39 40 SG79 SG80 118 119 143 142 141 GR2 GR3 120 GR24 119 15 SI/SO SCK STB MCU 14 13 PT6314 27 28 29 RL1 RL2 /CLR /RESET DLS DS1 DS0 IFSET OSC2 OSC1 VDD2 VDD2 VDD1 39 38 VSS1 VSS1 VSS2 1 36 50V 34 35 3 5V 56K 56 5V 7 9 10 11 24 PT6314 V1.3 - 44 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 APPLICATION CIRCUIT 2: I80 INTERFACE 143 GR1 142 GR2 141 GR3 120 GR24 5 x 8 dot x 24Grid x 2 Line VFD SG2 SG3 39 40 SG79 SG80 118 119 143 142 141 GR2 GR3 12 /WR 13 RS 14 /RD 16 DB0 23 27 28 29 DB7 RL1 RL2 /CLR /RESET DLS DS1 DS0 120 GR24 119 MCU PT6314 IFSET OSC2 OSC1 VDD2 VDD2 VDD1 39 MPU 38 VSS1 VSS1 VSS2 1 36 50V 34 35 3 5V 56K 56 5V 7 9 10 11 24 25 PT6314 V1.3 - 45 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 APPLICATION CIRCUIT 3: M68 INTERFACE 143 GR1 142 GR2 141 GR3 120 GR24 5 x 8 dot x 24Grid x 2 Line VFD SG2 SG3 39 40 SG79 SG80 118 119 143 142 141 GR2 GR3 12 R/W 13 RS 14 E 16 DB0 23 27 28 29 DB7 RL1 RL2 /CLR /RESET DLS DS1 DS0 120 GR24 119 MCU PT6314 IFSET OSC2 OSC1 VDD2 VDD2 VDD1 39 MPU 38 VSS1 VSS1 VSS2 1 36 50V 34 35 3 5V 56K 56 5V 7 9 10 11 24 25 PT6314 V1.3 - 46 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 ORDERING INFORMATION Order Part Number PT6314-001 PT6314-002 PT6314-16 PT6314-001 (L) PT6314-002 (L) PT6314-16 (L) Package Type 144 Pins, LQFP 144 Pins, LQFP 144 Pins, LQFP 144 Pins, LQFP 144 Pins, LQFP 144 Pins, LQFP Top Code PT6314-001 PT6314-002 PT6314-16 PT6314-001 PT6314-002 PT6314-16 Notes: 1. (L), (C) or (S) =Lead Free. 2. The Lead Free mark is put in front of the date code. PT6314 V1.3 - 47 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC PT6314 PACKAGE INFORMATION 144 PINS, LQFP (BODY SIZE: 20 X 20MM, PITCH SIZE: 0.50MM, THK BODY: 1.40MM) D D1 -DA A2 A1 E1 E -A- -B- L1 e 1 b c C SEATING PLANE ccc C 2 R1 -HR2 GAUGE PLANE 0.25mm S L 3 PT6314 V1.3 - 48 - March, 2006 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw Dot Character VFD Controller/Driver IC Symbol A A1 A2 b D D1 e E E1 1 2 3 C L L1 R1 R2 S ccc Min. 0.05 1.35 0.17 Nom. 1.40 0.22 22.00 BSC. 20.00 BSC. 0.50 BSC. 22.00 BSC. 20.00 BSC. 3.5 o 12 o 12 o 0.60 1.00 REF. 0.08 Max. 1.60 0.15 1.45 0.27 PT6314 0o 0o 11 o 11 o 0.09 0.45 0.08 0.08 0.20 7o 13 o 13 o 0.20 0.75 0.20 - Notes: 1. Controlling Dimensions are in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. 3. The top packge body size may be smaller than the bottom package size by as much as 0.15mm. 4. Datums A-B and D to be determined at datum plane H. 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 6. Details of pin1 identifier are optional but must be located within the zone indicated. 7. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. 8. A1 is defined as the distance from the seating plane to the lowest point on the package body. 9. Refer to JEDEC STD MS-026 Variation BFB JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION PT6314 V1.3 - 49 - March, 2006 |
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